Researchers have been making significant advancements in developing low-power and high-density DRAM technology, as evidenced by a series of papers presented at various IEEE conferences between 2020 and 2024.
A team led by Belmonte demonstrated a capacitor-less, long-retention DRAM cell that opens the door to monolithic 3D DRAM with >400s retention. In subsequent work, they tailored IGZO-TFT architecture for capacitorless DRAM, achieving >103s retention, >1011 cycles endurance, and scalability down to 14nm. They also achieved the lowest IOFF in capacitorless DRAM through reactive ion etching of IGZO-TFT.
Other researchers, such as Chen, Liao, and Lee, focused on improving multi-bit statistics and density of DRAM cells through various techniques such as dual-gate IGZO 2T0C DRAM, 4F2 multi-bit dual-gate 2T0C DRAM, and bit-cost-scalable 3D DRAM architecture.
Further work by Hu and Ye optimized IGZO FETs for high-density DRAM with impressive retention times and 3-bit operation capabilities. Meanwhile, researchers like Liu and Athena have been exploring novel approaches such as integrating gain cell memory on logic platforms and developing complementary gain cell memory using oxide semiconductors.
Additionally, studies by Chasin have contributed to understanding and modeling the reliability of thin-film IGZO transistors and unraveling the impact of device architecture, channel film deposition methods, and operating conditions on IGZO device reliability.
These advancements in DRAM technology are crucial for improving memory storage capabilities in various electronic devices while reducing power consumption and increasing density. The research presented in these papers highlights the cutting-edge innovations in the field of DRAM technology and lays the foundation for future advancements in memory storage technology.
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